As semiconductor technology advances into the deep sub-micron process nodes, short channel effects can severely degrade performance. The carrier velocity saturates in such short channels, which slows switching speeds and reduces transistor strength. To achieve high density yet have adequate transistor strength, strain engineering techniques have been developed so that the crystal lattice for the semiconductor substrate is strained in the diffusion region used to form the transistor source and drains. The diffusion region is typically referred to as oxide diffusion or “OD” with regard to transistor layout terminology. In other words, the OD is not only doped n-type or p-type as appropriate to achieve the desired transistor type (NMOS or PMOS) but is also strained to increase carrier velocity and transistor strength.
A local strain for just the diffusion regions has proven to be superior as compared to the use of a global strain across the entire substrate. The type of local strain depends upon the transistor type. The diffusion region for a PMOS transistor is compressively strained whereas the diffusion region for an NMOS transistor has tensile strain. For example, a film of SiGe may be applied to a p-type diffusion region to introduce compressive strain whereas a film of SiN may be applied to an n-type diffusion region to introduced tensile strain. The resulting strain engineering of silicon has proven to be quite successful for the achievement of satisfactory transistor strength in deep sub-micron process nodes.
Strain engineering on the diffusion regions introduces a number of constraints into the layout process. FIG. 1 illustrates the layout for an example pair of transistors. A first transistor 100 has its source (S) and drain (D) defined by a first diffusion region 105. A polysilicon gate 110 separates the source and drain regions. Diffusion region 105 spans underneath polysilicon gate 110 between the source and drain regions to form a channel for first transistor 100. A similar arrangement of another diffusion region 115 and polysilicon gate 120 defines a second transistor 101. At advanced process nodes, the layout of FIG. 1 would be inefficient because the diffusion regions 105 and 115 are relatively short. Such a short length for a diffusion region allows its crystal lattice to relax too much despite the use of local strain engineering. Transistors 100 and 101 would thus be too weak. In contrast, if diffusion regions 105 and 115 could be extended as shown by the dotted lines 125 to form a continuous diffusion region, there would be increased local strain and thus better performance. But such an extension for diffusion regions 105 and 115 would short the drain of first transistor 100 to the source of second transistor 101.
To achieve satisfactory transistor performance in the deep sub-micron process nodes, “continuous OD” layouts have been developed. FIG. 2 illustrates an example continuous diffusion region layout for a diffusion region 200. Transistors 100 and 101 are still defined with respect to polysilicon gates 110 and 120, respectively. But diffusion region 200 is continuous for both transistors such that it can develop adequate lattice strain for satisfactory transistor strength. A blocking transistor 201 defined with regard to a polysilicon gate 205 electrically isolates transistors 100 and 101 by being configured to be always turned off For example, if diffusion 200 is doped p-type, blocking transistor 201 is a PMOS transistor such that polysilicon gate 205 would be tied to the power supply voltage VDD to isolate transistors 100 and 101 from each other. Alternatively, if diffusion region 200 is doped n-type, blocking transistor 201 is an NMOS transistor such that polysilicon gate 205 would be tied to ground to isolate transistors 100 and 101.
Although the use of continuous OD enables sufficient crystal lattice strain to be achieved, the charging of the gates for the blocking transistors complicates the layout. To perform this charging, local interconnects are used to couple from power (or ground) metal layers to the gate layers for the blocking transistors. The layout of the local interconnects for the blocking transistors has proven to be awkward and decreases density.
Accordingly, there is a need in the art for improved local interconnect layouts.